Organizing Committee
General Co-Chairs Rubin Parekhji (TI, IN) MS Gaur (MNIT, IN)
Program Co-Chairs Michiko Inoue (NAIST, JP) Virendra Singh (IISc, IN)
Finance Chair Vijay Laxmi (MNIT, IN)
Publication Chair (BESU, IN)
Publicity Chair Chia Yee Ooi (UTM, MY) Zhiqiang You (Hunan U., CN)
Local Organization Chair Lava Bhargava (MNIT, IN)
Registration Chair Jaynarayan Tudu (IISc, IN) Ashok Sihag (GBU, IN)
Web Site Chair Pawan Kumar (IISc, IN)
Steering Committee Tomoo Inoue (JP) – Chair Dong Xiang (CN) – Vice-Chair Hideo Fujiwara (JP) Masaki Hashizume (JP) Toshinori Hosokawa (JP) Kazuhiko Iwasaki (JP) Erik Larsson (SE) Xiaowei Li (CN) Alex Orailoglu (US) Kewal Saluja (US) Virendra Singh (IN) Hideo Tamamoto (JP) Dafang Zhang (CN) |
WRTLT’11 |
The purpose of this workshop is to bring researchers and practitioners on VLSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. The twelfth workshop on RTL and high level testing (WRTLT'11) will be held in conjunction with the 20th Asian Test Symposium (ATS'11). The workshop aims to encourage the presentation and discussion of truly innovative and “out-of-the-box” ideas aimed at addressing these challenges of high level test. We hope the workshop will provide an ideal forum for future complex system test at higher level of abstraction. Representative topics include, but not limited to: |
IEEE Twelfth Workshop on RTL and High Level Testing 2011 MNIT Jaipur, India November 25-26, 2011 |
Submission Details: To present at the Workshop, authors are invited to submit previously unpublished technical proposals. The proposals must be full papers of maximum 8 pages or an extended summary. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address. Submit a copy of your proposal by PDF, via easy chair or via E-mail to : wrtlt2011@serc.iisc.ernet.in
Important Dates: Paper Submission: August 31, 2011 (Extended) Author Notification: September 25, 2011 Final Paper Submission: October 15, 2011
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· Functional fault modeling · Microprocessor testing · Relationship between RTL and gate-level testing · High level test bench generation · High level approaches for testing |
· RTL ATPG · RTL BIST · Design Verification · SoC/NoC Testing · Secure Testing · 3D IC Test |