IEEE Twelfth Workshop on RTL and High Level Testing 2011

MNIT Jaipur, India November 25-26, 2011

Call for Papers (pdf)


The purpose of this workshop is to bring researchers and practitioners on VLSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. The twelfth workshop on RTL and high level testing (WRTLT'11) will be held in conjunction with the 20th Asian Test Symposium (ATS'11). The workshop aims to encourage the presentation and discussion of truly innovative and “out-of-the-box” ideas aimed at addressing these challenges of high level test. We hope the workshop will provide an ideal forum for future complex system test at higher level of abstraction.

Representative topics include, but not limited to:

Submission Details:

To present at the Workshop, authors are invited to submit previously unpublished technical proposals. The proposals must be full papers of maximum 8 pages or an extended summary. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords.  Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address. Submit a copy of your proposal by PDF, via easy chair or via E-mail to : wrtlt2011@serc.iisc.ernet.in


Proposals for panel discussions are also invited.

Submissions are due no later than August 31, 2011 (Extended). Authors will be notified of the disposition of their presentation by September 25, 2011. Authors of accepted presentations must submit the final paper by October 15, 2011 for inclusion in the Workshop Proceedings, which will be provided to the attendees.



For Program Related Information

Michiko Inoue, NAIST, Japan

(kounoe at is dot naist dot jp)

Virendra Singh, IISc, Bangalore, India

(viren at serc dot iisc dot ernet dot in)



· Functional fault modeling

· Microprocessor testing

· Relationship between RTL and gate-level testing

· High level test bench generation

· High level approaches for testing



· Design Verification

· SoC/NoC Testing

· Secure Testing

· 3D IC Test