The Thirteenth Workshop on RTL and High Level Testing
November 22-23, 2012, Toki Messe Niigata Convention Center, Niigata, Japan
In conjunction with the 21st Asian Test Symposium (ATS'12)

WRTLT'12 Program
Visa Guide
Call for Papers
Related Links

Latest News!

Registration Desk and Hours

November 22, 11:30~18:00
November 23, 8:30~16:00

Entrance of Room 201B(2F)
(See Guide Map Here)

Keynote Address
(more detail: click the title!)
"Hardware Trojans: Threats and Emerging Solutions"
R. S. Chakraborty (Indian Institute of Technology, Kharagpur)

Invited Talk (more detail: click the title!)
"TRUDEVICE: a COST Action in Europe"
I. Polian (University of Passau)

"The Past and Future of WRTLT"
Y. Min (Chinese Academy of Sciences), H. Fujiwara (Osaka Gakuin University)

"System Level Testing Considerations as we Move from RTL to ESL"
Z. Navabi (University of Tehran)

Visa Guide information is now available!
WRTLT'12 Organizing Committee will send visa letters (confirmation letters)  to attendees requesting them.
Please contact Registration Chair (e-mail:
namba@ieee.org) if you request visa letters.


IEEE Computer Society Test Technology Technical Council

The IEICE Information and Systems Society,
Technical Committee on Dependable Computing

The purpose of this workshop is to bring researchers and practitioners of LSI testing from all over the world together to exchange ideas and experiences in register transfer level (RTL) and high level testing. WRTLT'12, the thirteenth workshop, will be held in conjunction with the 21st Asian Test Symposium (ATS'12) in Niigata, Japan. We hope and expect this workshop provides an ideal forum for frank discussion on this important topic for the future system-on-a-chip(SoC) devices and 3D ICs. Areas of interest include but are not limited to:

- High level Testing : RTL/Behavior level testing, High level approaches for testing, RTL ATPG, RTL DFT, RTL BIST, High level synthesis for testability, Relationship between RTL and gate level testing, Functional fault modeling,
- High level test bench generation
- 3D IC Testing
- SoC/Noc Testing: Test scheduling, Core testing, Interconnect testing
- Reliable SoC : System level reliability, Self repair, Fault tolerant SoC
- Microprocessor Testing
- Design Verification

- Gate Level Test Related Issues : Low power testing, Test compression, ATPG, DFT, BIST
- Secure Testing
- Hardware Trojan Detection

Authors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper and should include: title, full name and affiliation of all authors, 50 words abstract, keywords and the name of contact author. All submissions are now to be made electronically through the EasyChair conference system. Detailed instructions for submissions are to be found the website. Electronic submissions in PDF files are strongly recommended. Please visit the following website for submissions.

Photocopies of accepted papers will be handed out to the attendees at the workshop site.

  • Submission deadline: Sep. 9, 2012
  • Notification of acceptance: October 1, 2012
  • Camera ready due: October 26, 2012
  • Workshop days: November 22-23, 2012