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Final Program Friday, October 12, 2007
(Meeting Room No. 3, Building 8) 8:30~9:30
Welcome Messages WRTLT'06 Best Paper Award Invited Talk: Modular Testing of System-on-Chip Integrated Circuits: Recent Advances and Bold Predictions. Krishnendu Chakrabarty (Duke University, USA) 9:30~10:20
Session 1 RTL Testing Session Chair: Kazuhiko Iwasaki (Tokyo Metropolitan University, Japan)
1.1 RTL Don't Care Path Identification and Synthesis for Transforming Don't Care Paths into False Paths Yuki Yoshikawa1, Satoshi Ohtake, Hideo Fujiwara
1.2 An Extended Class of Acyclically Testable Circuits Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
10:20~10:50
Coffee break & Poster Session
10:50~12:00
Session 2 Design Verification Session Chair: Jaan Raik (Tallinn University of Technology, Estonia)
2.1 Design Verification of an embedded Processor: From Error Model to Test Method Tao Lv, Yang Zhao, Hua-wei Li, Xiao-wei Li
2.2 Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits Andre Sulflow, Ulrich kuhne, Robert Wille, Daniel Grobe, Rolf Drechsler
2.3s Accelerating Assertion Based Verification with FPGA Co-processing Rob Quigley, Damian Dalton, Christian Steger
12:00~13:30
(First Floor, Friendship Palace) Lunch
12:00~13:30 (VIP Room, Building 8) WRTLT Steering Committee Meeting
13:30~14:20
Session 3 Fault Tolerance and Diagnosis Session Chair: Yu Huang (Mentor Graphics Corporation, USA)
3.1 Cost-Efficient Selection of Gates for Circuit Hardening Based on Critical Soft Error Rate Ilia Polian, John P. Hayes, Bernd Becker
3.2 A Design-for-Diagnosis Technique for Diagnosing Integrated Circuit Faults with Faulty Scan Chains Fei Wang, Yu Hu, Xiaowei Li
14:20~14:50
Coffee break & Poster Session
14:50~16:00
Session 4 Test Compression and BIST Session Chair: Ilia Polian (Albert-Ludwigs-University, Germany)
4.1 Improvement in Test Compression for IP Core Testing Using Reconfigurable Network Kazuteru Namba, Yoshikazu Matsui and Hideo Ito
4.2 A Case Study of SoC Test Resource Partitioning Using Modular Embedded Deterministic Test (EDT) Flow David Hong, Fiona Zhou, Yu Huang, Wu Yang, Actel Niu
4.3s The Implementation Built-In Self Tests in a Digital Radio Processor (DRPTM) Cui Mao, Deepa Mannath, Besong Val, Oren Eliezer, Scott Larson
16:00~17:30
Panel Session:
Title: Multi-Core Microprocessor Chip Verification and Test: Are They As Scalable As Design?
Organizer: Hideo Fujiwara (Nara Institute of Science and Technology, Japan)
Moderator: Alex Orailoglu (University of California - San Diego, USA)
Panelists:
Kazumi Hatayama (STARC, Japan) Zainalabedin Navabi (Tehran University, Iran) Yu Huang (Mentor Graphics Corporation, USA) Sying-Jyan Wang (National Chung-Hsing University, Taiwan) Krishnendu Chakrabarty (Duke University, USA)
17:30~18:30
(First Floor, Friendship Palace) Dinner 18:30~21:20
(Laoshe Tea House) Social Event Saturday, October 13, 2007
(Meeting Room No. 3, Building 8) 8:30~9:10
Invited Talk: Challenges and Solutions for the Design of Fault-Tolerant Systems Zebo Peng (Linkoping University, Sweden)
9:10~10:20
Session 5 RTL Testing Session Chair: Tomoo Inoue (Hiroshima City University, Japan)
5.1 A Test Generation Methods for State Observable FSMs to Increase Defect Coverage Under Test Length Constraint Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwar
5.2 Register allocation scheme based on behavioral testability analysis with scheduling for easy testability Benmao Cheng, Hong Wang, Shiyuan Yang, Daoheng Niu, Yang Jin
5.3s A New RTL Fault Model Yiqiong Ding, Jianhui Jiang
10:20~10:40
Coffee break
10:40~12:00
Panel Session:
Title: Defect-Tolerance, Error-Tolerance: Which way to go? How?
Organizer: Qiang Xu (Chinese University of Hong Kong, China)
Moderator: Sudhakar M. Reddy (University of Iowa, USA)
Panelists: Sandeep Gupta (University of Southern California, USA) Illia Polian (Albert-Ludwigs-University, Germany) Abhijit Chatterjee (Georgia Institute of Technology, USA) Zebo Peng (Linkoping University, Sweden)
12:00~13:00
(First Floor, Friendship Palace) Lunch
13:00~14:10
Session 6 Design Verification and DFT Session Chair: Rolf Drechsler (University of Bremen, Germany)
6.1 Abstraction of Word-level Polynomial Function from Arithmetic Transform for Arithmetic Datapath Donghai Li, Guangshun Li, ,Guangsheng Ma, Jing Hu
6.2 Assertion Checking with PSL and High-Level Decision Diagrams Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar
6.3s A Testable and Repairable Design of Continuous-Time Filters Hu Geng, Wang Hong, Yang Shiyuan
14:10~14:30
Coffee break
14:30~15:40
Session 7 Crosstalk and Nano-Device Faults Session Chair: Sandeep Gupta (University of Southern California, USA)
7.1 Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Transmission Guihai Yan, Yinhe Han, Xiaowei Li, Hui Liu
7.2 MT Compacted Set for Interconnect Crosstalk on SOC Zhang Ying, Li Huawei, Li Xiaowei
7.3s A Fault Model for Single Electron Devices S. Kundu, J. Mahata, S. Roy
15:40~16:55 Session 8 Scan Based Testing and ATE Session Chair: Qiang Xu (Chinese University of Hong Kong, China)
8.1 Don't Care Filling to Reduce Leakage Power in VLSI Circuit Testing Tapas Kr. Maiti, Santanu Chattopadhyay
8.2 Tester Structure Expression Language and Its Application to Tester Selection Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa
8.3 On SoC Testing Using Multiple Scan Chains with Scan Tree Configurations Hiroyuki Yotsuyanagi, Takeshi Iihara, Masaki Hashizume
16:55~17:05
Closing session
Announcement of WRTLT'08
E-mail: wrtlt07@ict.ac.cn |