WRTLT'09 Advance Program November 27--28, 2009 November 27 (Friday) Registration 8:00 -- 8:40 . Opening session 8:40 -- 9:00 Keynote speech 9:00 -- 10:00 System-Level Verification and Test: From Microprocessors to SoCs and Multicore Chips Jacob Abraham (UT Austin -- USA) Coffee break 10:00 -- 10:30 Session 1 RTL and High-Level Testing 10:30 -- 11:50 Chair: Tomoo Inoue (Hiroshima City University -- Japan) 1.1 A DFT Method for Functional Scan at RTL Marie Engelene, J. Obien and Hideo Fujiwara ( Nara Institute of Science and Technology -- Japan) 1.2 Observation-Point Selection at Register-Transfer Level to Increase Defect Coverage for Functional Test Sequences Hongxia Fang 1, Krishnendu Chakrabarty 1 and Hideo Fujiwara 2 ( 1 Duke University - USA, 2 Nara Institute of Science and Technology -- Japan) 1.3 A Study of Software-Level Delay Fault Simulation for JPEG Decoder Application on CMP Shun-Yen Lu, Tso-Hua Chien and Jing-Jia Liou ( National Tsing Hua University -- Taiwan) 1.4 Path-Based Resource Binding to Reduce Delay Fault Test Cost Michiko Inoue, Satoshi Ohtake, Yu-ichi Uemoto, and Hideo Fujiwara ( Nara Institute of Science and Technology -- Japan) Lunch & Poster 12:00 -- 13:30 Invited talk 13:30 -- 14:15 A research perspective on post-silicon validation and debug Nicola Nicolici (McMaster Univ. -- Canada) Session 2 Low-Power Testing 14:20 -- 15:20 Chair: Xiaoqing Wen (Kyushu Institute of Technology -- Japan) 2.1 Low Capture Power Adjacent Fill (LCPAF) in Test Data Compression Environment Jia Li 1, Qiang Xu 2 and Dong Xiang 1 (1 Tsinghua University - China, 2 The Chinese University of Hong Kong - Hong Kong) 2.2 Scan Cells Reordering to Minimize Peak Power during Scan Testing of SoC Jaynarayan T Tudu 1, Erik Larsson 2, Virendra Singh 1, and Hideo Fujiwara 3 (1. Indian Institute of Science -India, 2. Linkoping University - Sweden, 3. Nara Institute of Science and Technology -- Japan) 2.3 Efficient Modeling of IR-Drop Using Dynamic SDF for Test and Diagnosis Ke Peng 1, Yu Huang 2, Wu-Tung Cheng 2, and Mohammad Tehranipoor 1 (1 University of Connecticut -- USA, 2 Mentor Graphics -- USA) Coffee break 15:20 -- 15:40 Session 3 Fault Simulation and Test Generation 15:40 -- 17:00 Chair: Jing-Jia Liou ( National Tsing Hua University -- Taiwan) 3.1 A Fast and Memory-Efficient Fault Simulation Using GPU Dawen Xu, Yinhe Han, Huawei Li, and Xiaowei Li ( Chinese Academy of Sciences -- China) 3.2 Test Generation for Open Faults Considering the Effects of Adjacent Lines Ryota Kuribayashi, Hiroyuki Yotsuyanagi, and Masaki Hashizume ( The Univ. of Tokushima -- Japan) 3.3 Compact Test Generation for Complete Coverage of Path Delay Faults in a Standard Scanned Circuit Dong Xiang and Zhen Chen ( Tsinghua University - China) 3.4 X-Identification According to Required Distribution for Industrial Circuits Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen,and Seiji Kajihara (Kyushu Institute of Technology -- Japan) Panel 17:00 -- 18:30 Test / Diagnosis at Multi-Core / Multi-Die Era Organizer and Moderator: Yu Huang (Mentor Graphics -- USA) Panelists: Kazumi Hatayama (STARC -- Japan) Zebo Peng (Linkoping University -- Sweden) Yasuo Sato (Kyushu Institute of Technology -- Japan) James Chien-Mo Li (National Taiwan University -- Taiwan) Ilia Polian (Albert Ludwigs University of Freiburg -- Germany) Social Event 18:30 -- 22:30
November 28 (Saturday) Invited talk 8:30 -- 9:15 Quality, Cost and Time-to-Market: We Need Them All Xinli Gu (Cisco -- USA) Session 4 Design for Testability 9:20 -- 11:00 Chair: Ilia Polian (Albert Ludwigs Univ. of Freiburg -- Germany) 4.1 Is the Full Scan Design Unshakeable? Yinhua Min (Chinese Academy of Sciences -- China) 4.2 A Design of Concurrently Testable Response Analyzers in Built-in Self-Test Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara,and Tomoo Inoue (Hiroshima City University -- Japan) 4.3 A Low Cost Self-Hold Analog Test Wrapper Design for Mixed-Signal SOCs Yang Jin, Hong Wang, and Shiyuan Yang (Tsinghua University - China) 4.4 Improving Transition Delay Fault Coverage with Partial Enhanced Scan Technique Songwei Pei, Huawei Li, and Xiaowei Li (Chinese Academy of Sciences -- China) 4.5 Scan Slice Compression Technique Using Dynamical Updating Reference Slices Jun Liu, Yinhe Han, and Xiaowei Li (Chinese Academy of Sciences -- China) Coffee break 11:00 -- 11:20 Session 5 Diagnosis and Fault-Tolerance 11:20 -- 12:40 Chair: Huawei Li (Chinese Academy of Sciences -- China) 5.1 Diagnosis of Logic-chain Bridging Faults #Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin,and James Chien-Mo Li (National Taiwan University -- Taiwan) 5.2 An Even-Odd DFD Technique for Scan Chain Diagnosis Venkat Rajesh A 1, Erik Larsson 2,Virendra Singh 3, and MS Gaur 1 (1 Indian Institute of science - India, 2 Linkoping University - Sweden, 3 Malaviya National Instituet of Technology -- India) 5.3 Transition Fault Diagnosis Using At-speed Test Patterns Shang-Feng Chao, Jheng-Yang Ciou, and James Chien-Mo Li (National Taiwan University -- Taiwan) 5.4 On Predicting the Maximum Circuit Aging Song Jin, Yinhe Han, Huawei Li, and Xiaowei Li (Chinese Academy of Sciences -- China) Poster 1 The Impact of Performance Asymmetry on Topology Reconfiguration in NoC-based Many-core Systems Yue Yu 1, Lei Zhang 1, Jianbo Dong 1, Yinhe Han 1, and Shangpin Ren 2 (1 Chinese Academy of Sciences - China, 2 Illinois Institute of Technology -- USA) 2 A Thermal-aware Parallel Multicast Testing Method Based on Many-core Chips Fang Fang 1, Wei Wang 1, Yinhe Han 2, and Xiaowei Li 2 (1 Hefei University of Technology - China, 2 Chinese Academy of Sciences - China) 3 A Particle Swarm Optimization-based BPNN Approach for Fault Diagnosis of Analog Electronic Circuits Wenji Zhu and Yigang He (Hunan University -- China) 4 Microprocessor Modeling for Board Level Test Access Automation Sergei Devadze 1, Artur Jutman 1, Anton Tsertov 2, and Raimund Ubar 2 (1 Testonica Lab Ou¨ - Estonia, 2 Tallinn Univ. of Technology -- Estonia) 5 Hierarchical Formal Verification Method based on Transactions Zhiqiu Kong, Jinian Bian, Yanni Zhao, and Shujun Deng (Tsinghua University - China) 6 Semi-Confliction Guided Problem Partitioning Algorithm in FPGA-based SAT Solver Zhongda Yuan and Jinian Bian (Tsinghua University - China) 7 A Low Power Test Scheme Based on Segment Fixing Folding Counter Tian Chen, Hua-guo Liang, Min-sheng Zhang, Wei Wang, and Mao-xiang Yi (Hefei University of Technology - China) 8 SORPECO: Localized SOR Analysis Method for Power/Ground Networks in ECO Placements Zuying Luo 1, Guoxing Zhao 1, and Jinhe Zhou 2 (1 Beijing Normal University - China, 2. Beijing Information Science and Technology University -- China) 9 Modeling Test Flows of Automated Test Equipment Test Program Using Simple Graph Hui Jia Tai 1, Chin Kuan Ho 1, Hze Horng Ong 2, Somnuk Phon-Amnuaisuk 1, Siew Beng Thum 2 (1 Multimedia University - Malaysia, 2 Intel Corporation, -- Malaysia) 10 A Model for Scan Insertion at the Register Transfer Level
Lilia Zaourar 1, Yann Kieffer 1, Chouki Aktouf 2, Vincent Juliard 2 (1 G-SCOP laboratory - France, 2 DeFacTo Technologies -- France)
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