Keynote Adress
"Hardware Trojans: Threats and Emerging Solutions"
(Plenary Session 1; 13:25-14:25, Nov. 22, 2012)
Rajat Subhra Chakraborty
(Indian Institute of Technology, Kharagpur)
Summary: Economic reasons dictate the widespread participation of external agents
in modern design and manufacture of integrated circuits (ICs), which decreases
the control that the IC design houses used to traditionally have over their
own designs. In this scenario, malicious, hard-to-detect circuit modifications
made during the design or manufacturing steps, commonly known as "hardware
Trojans" have emerged as a major security concern. This issue raises
the question of ensuring Trust in an integrated circuit, and whether the
entire design and manufacturing flow can be certified to be secure. A satisfactory
answer to this question is of paramount importance in gaining trust about
the result of the information processing carried out by the systems of
which the ICs are a part. In this tutorial, we would explore the threat
posed by Hardware Trojans, and testing techniques to detect them.
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Biography: Dr. Rajat Subhra Chakraborty is an Assistant Professor in the Computer
Science and Engineering Department of IIT Kharagpur, India. He has a Ph.D.
in Computer Engineering from Case Western Reserve University, USA. His
professional experience includes a stint as CAD Software Engineer at National
Semiconductor (India Design Centre), and a graduate internship at Advanced
Micro Devices (AMD). His primary research interest is hardware security,
including design methodology for hardware IP/IC protection, hardware Trojan
detection/prevention through design and testing, attacks on hardware implementation
of cryptographic algorithms, and reversible watermarking for digital content
protection. He has close to 40 publications in international journals and
conferences of repute. He has delivered tutorials at several international
conferences and workshops, and has rendered his service as a reviewer and
program committee member for multiple international conferences and journals.
He is the co-author of one book on hardware security (forthcoming). He
is a recipient of the "IBM Faculty Award" for 2012. Two patents
have been filed based on his research work. Dr. Chakraborty is a member
of IEEE.
Invited Talks
"TRUDEVICE: a COST Action in Europe"
(Plenary Session 1; 13:25-14:25, Nov. 22, 2012)
Ilia Polian (University of Passau)
Summary: Hardware security is becoming increasingly
important for many embedded systems applications ranging from small RFID tag to
satellites orbiting the earth. Its relevance is expected to increase in the
upcoming decades as secure applications such as public services, communication,
control and healthcare will keep growing.
The vulnerability of hardware devices that implement cryptography
functions (including smart cards) has become the Achille’s heel in the last
decade. Therefore, the industry is recognizing the significance of hardware
security to combat semiconductor device counterfeiting, theft of service and
tampering.
The
recently approved COST Action “Trustworthy Manufacturing and Utilization of
Secure Devices” aims at creating a European network of competence and experts
on all aspects of hardware security including design, manufacturing, testing,
reliability, validation and utilization. The network will play a key role in
developing solutions responding to the hardware security challenges.
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Biography: Ilia Polian
is a Full Professor of Computer Engineering and the Vice Dean of Faculty of
Informatics and Mathematics at the University of Passau, Germany. He received
his PhD degree in 2003 from the University of Freiburg, Germany. His research
interests include test methods, robustness, security, and quantum circuits. He
is IEEE Senior member, has over 100 publications, won one best paper award and
one best paper award nomination. He was involved in organization of several
conferences, including IEEE European Test Symposium 2007 in Freiburg and Test
Methods and Reliability workshop 2011 in Passau. He is Vice Chair of the German
(GI/VDE/VDI) focus group on Test Methods and Reliability.
"The Past and Future of WRTLT"
(Plenary Session 2; 9:00-10:10, Nov. 23, 2012)
Yinghua Min (Chinese Academy of Sciences)
Hideo Fujiwara (Osaka Gakuin University)
Summary: The paper recalls the establishment, and
development of the IEEE workshop on RTL and High Level Testing. This workshop has run for 12 years,
and has brought researchers and practitioners of LSI testing from all over
the world together to exchange ideas and experiences inregister transfer level (RTL) and high level testing. However, since nano-scale
ICs are confronting material and fabrication technology challenges, it
might be hard for computer scientists to provide new ideas on this kind of ICs testing. In addition, many people pay attention
to paper publication, which is not a major issue for aworkshop. In order to re-activate the workshop, authors suggest some ideas for consideration.
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Biography: YINGHUA MIN graduated from Mathematics Department of Jilin University in1962,
and completed his post-graduate study at China Academy of Railway Sciences
in 1966. He has visited Stanford and other universities in the US for years
since 1981. He is now an emeritus professor of Computer science at Institute
of Computing Technology, Chinese Academy of Sciences, the honorary Chair
of technical committee on fault-tolerant computing, China Computer Federation.
He published 250 technical papers, and 4 books, and received the Natural
Science awards three times from the Chinese Academy of Sciences. He served
on the editorial board of Journal of Electronics Testing, and as the Executive
Editor-in-Chief of Journal of Computer Science and Technology. He was a
member of IEEE CS Fellow Committee and numerous program committees of IEEE
international conferences, the general co-chair of IEEE ATS'98 in Singapore
and IEEE PRDC'99 in Hong Kong, and was the steering committee chair of
IEEE WRTLT and received the meritorious service award from IEEE Computer
Society in 2001. His current research interests include electronic testing,
dependable computing, software reliability, and networking. He is a Fellow
of IEEE, and a golden core member of IEEE CS.
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Biography: HIDEO
FUJIWARA received the B.E., M.E., and Ph.D. degrees in electronic engineering
from Osaka University, Osaka, Japan, in 1969, 1971, and 1974,
respectively. He was with Osaka
University from 1974 to 1985, Meiji University from 1985 to 1993, Nara
Institute of Science and Technology (NAIST) from 1993 to 2011, and joined Osaka
Gakuin University in 2011. Presently he is Professor Emeritus of NAIST and a
Professor at the Faculty of Informatics, Osaka Gakuin University, Osaka, Japan. He has published over 400 papers in refereed
journals and conferences, and nine books including the book from the MIT Press
(1985) entitled “Logic Testing and Design for Testability.” He received several awards such as IEEE
Computer Society Meritorious Service Awards in 1996 and 2005, IEEE Computer Society Continuing Service
Award in 2005, and IEEE Computer Society Outstanding Contribution Award in 2001
and 2009. Dr. Fujiwara is a life fellow
of the IEEE, a Golden Core member of the IEEE Computer Society, a fellow of the
IEICE and a fellow of the IPSJ.
"System Level Testing Considerations as we Move from RTL to ESL"
(Plenary Session 2; 9:00-10:10, Nov. 23, 2012)
Zainalabedin Navabi (University of Tehran)
Summary: In the last fifty years, design abstraction level has change from gate
to RT- level, and now to ESL (Electronic System Level). In this path, new
design and test methods evolve, and the older methods became too cumbersome
and impractical for the complex new applications. Digital designers have
already established RT level design methods, and based on that, well established
test and testability methods have been put in place. Inspired from this,
we will be looking at ESL that is a new abstraction level in digital systems,
to find systematic methods of design and test. This talk focuses on ESL
test methods. This level of abstraction uses IP- cores for its processing
elements or components, and uses abstract channels for communicating between
these components. We consider how RT level DFT methods translate to this
new level of abstraction, and will look at test methods for testing communications
at this level.
Biography: Dr. Zainalabedin Navabi is a professor of Electrical and Computer Engineering
at the University of Tehran, and an adjunct professor at Worcester Polytechnic
Institute. Dr. Navabi is the author of several textbooks and computer based
trainings on VHDL, Verilog and related tools and environments. Dr. Navabi’s
involvement with hardware description languages begins in 1976, when he
started the development of a register-transfer level simulator for one
of the very first HDLs. In 1981 he completed the development of a synthesis
tool that generated MOS layout from an RTL description. Since 1981, Dr.
Navabi has been involved in the
design, definition and implementation of Hardware Description Languages. He has
written numerous papers on the application of HDLs in simulation, synthesis and
test of digital systems. He started one of the first full HDL courses at
Northeastern University in 1990. Since then he has conducted many short courses
and tutorials on this subject in the United States, Europe and Asia. Since
early 1990’s he has been involved in developing, producing, and broadcasting
online and video lectures on HDLs, Digital System Test, and various aspects of
automated design. In addition to being a professor, he is also a consultant to
CAE companies. Dr. Navabi received his M.S. and Ph.D. from the University of
Arizona in 1978 and 1981, and his B.S. from the University of Texas at Austin
in 1975. He is a senior member of IEEE, a member of IEEE Computer Society,
member of ASEE, and ACM.
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