--------------------- Advance Program -------------------------------------------------------- Workshop on RTL ATPG & DFT (WRTLT00) Changsha, Hunan, China Sept. 26-27,2000
Sponsored by IEEE COMPUTER SOCIETY TEST TECHNOLOGY TECHNICAL COUNCIL In cooperation with National Natural Science Foundation of China Technical Committee on Fault-Tolerant Computing, China Computer Federation Hosted by Hunan University
Workshop Web Page: http://cs.hunu.edu.cn/wrtlt, http://wrtlt.home.chinaren.com
Advance Program Monday, September 25, Dolton Hotel Registration: Dolton Hotel, 8:00-21:00 Reception: Dolton Hotel, 19:00-21:00
Tuesday, September 26, Hunan University Session 1: Opening session 9:00-11:00, at Yuelu Academy, Hunan University. Chair and Moderator: Yinghua Min, Institute of Computing Technology, CAS, China Keynote: “Design for Testability for Core-Based System-on-Chip” H. Fujiwara, Nara Institute of Science and Technology, Japan Inside tour: 11:00-12:00 at Yuelu Academy Lunch: 12:00, Hunan University Session 2: Test Generation (1), 13:30-15:00 Chair: Hideo Tamamoto, Akita University, Japan 2-1 “Test Generation and Design-for Testability Based on Acyclic Structure with Hold Registers” T. Inoue, et al., Hiroshima City University, Japan 2-2 “An Efficient Method for Behavioral RTL ATPG” Zhigang Yin, et al., Institute of Computing Technology, CAS, China 2-3 “A Parallel ATPG Algorithm Based on Big Functional Block Partitioning” Zhide Zeng, National University of Defense Technology, Changsha, China
Break: 15:00-15:30
Session 3: Scan Design (1), 15:30-17:00 Chair: Shiyi Xu, Shanghai University, China 3-1 “RTL Partial Scan Design System: REPS” T. Hosokawa, et al., Matsushita Electric Industrial Co., Ltd., Japan 3-2 “A Built-In Test Scheme for Pipelined Multipliers and Dividers” Hao-Yung Lo, et al., Feng Chia University, Tsing Hua University, Taiwan Tour and Dinner: 17:00-20:00 Yuelu Mountain
Wednesday, September 27, Dolton Hotel Session 4: Design for Testability (1), 8:30-10:00 Chair: Zhongcheng Li, Institute of Computing Technology, CAS, China 4-1 “A DFT Method for Single-Control Testability of RTL Data Paths for BIST” T.Masuzawa, et al., Nara Institute of Science and Technology, Japan 4-2 “A Non-Scan DFT Method at RTL Based on Fixed-Control Testability to Achieve 100% Fault Efficiency” S. Ohtake, et al., Nara Institute of Science and Technology, Japan
Coffee break: 10:00-10:30
Session 5: Scan Design (2), 10:30-12:00 Chair: Xiaowei Li, Peking University, China 5-1 “RTL Scan Design” Weikang Huang, Fudan University, Shanghai, China 5-2 “A Non-Scan Testable Design of Sequential Circuits by Improving Controllability” Hideo Tamamoto, et al, Akita University, Japan 5-3 “Verifying Stacks and Queues using Symbolic Simulation Techniques” Y. Morihiro, et al., Tokyo Institute of Technology, Tokyo, Japan Session 6: Test Generation (2), 13:30-15:00 Chair: K.Hatayama, Hitachi, Ltd., Japan 6-1 “A Forecasting and Evaluation System for Test Generation Algorithms” Shiyi Xu, Shanghai University, Shanghai, China 6-2 “Target-Fault-Oriented Test Generation of Sequential Circuits Using Genetic Algorithm” Li Shen, Institute of Computing Technology, CAS, Beijing, China 6-3 “A Structure-Oriented RTL ATPG” Xiaolu Huang et al., Hunan University, Changsha, China Coffee break : 15:00-15:30 Session 7: Design for Testability (2), 15:30-17:00 Chair: T. Inoue, Hiroshima City University, Japan 7-1 “Adding Transitions of Undefined States to State Transition Tables for Testability Enhancement” H. Yotsuyangagi, et al., The University of Tokushima, Japan 7-2 “IC Testing by Phase Classification Based on Behavioral Description of RTL” Huawei Li, et al., Institute of Computing Technology, CAS, Beijing, China Banquet and Entertainment: 19:00-21:00
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