WRTLT'02 Advance Program
Technical sessions are held at San Vitores & Magellan.
Wednesday, November 20 18:30-20:00 Welcome Reception
Thursday, November 21 8:30- 9:30 Opening Remarks and Invited Talk General Chair's Message T. Hayashi - Mie University PC Chair's Message K. Hatayama - Hitachi Ltd. Invited Talk - Native-Mode Built-In Self-Test J.A.Abraham - U. of Texas at Austin, USA 9:30-10:00 Coffee Break 10:00-11:40 Session 1: SoC Test S1-1 Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers E. Larsson, H. Fujiwara - NAIST, Japan S1-2 Optimal Bandwidth Allocation in Concurrent SoC Test Under Pin Number Constraints I. Polian, B. Becker - Albert-Ludwigs U., Germany S1-3 Design for Consecutive Transparency of RTL circuits T. Yoneda, H. Fujiwara - NAIST, Japan S1-4 Effective Test Program Induction for Microprocessor IP Core F. Corno, F. Cumani, M. Sonza Reorda, G. Squillero - Poli. de Torino, Italy 11:40-13:10 Lunch Time 13:10-14:50 Session 2: RTL DFT and BIST S2-1 A Non-scan DFT Method for RTL Data Path Circuits with Various Bit Width H. Date, T. Hosokawa, M. Miyazaki and M. Muraoka - STARC, Japan S2-2 A Partial Scan Design with Orthogonal Scan Paths T. Inoue - Hiroshima City U., Japan, H. Fujiwara - NAIST, Japan S2-3 Hierarchical BIST: Test-Per-Clock BIST with Low Overhead K. Yamaguchi, M. Inoue, H. Fujiwara - NAIST, Japan S2-4 Application of Partially Rotational Scan Technique to Processor Circuits K. Ichino, K. Watanabe, M. Arai, S. Fukumoto, K. Iwasaki - Tokyo Metropolitan U. 14:50-15:20 Coffee Break 15:20-17:00 Session 3: Test and Synthesis S3-1 Test Vector Overlapping for Test Cost Reduction in Core Testing T. Shinogi, Y. Yamada, T. Yoshikawa, S. Tsuruoka, T. Hayashi - Mie U., Japan S3-2 Defect Based Functional Test for Non-Volatile Memory Disturb Faults M. Mohammad, K. K. Saluja - U. of Wisconsin, USA S3-3 Monitoring for the Real Time Constraints C. Peng, B. Wu, X. Sun, Z. Chen - Fudan U., China S3-4 Simplification of Incomplete Specified Machine Based on Genetic Algorithm Implementing Dormant Mechanism M. Hashizume, T. Matsushima, T. Shimamoto, H. Yotsuyanagi, T. Tamesada - U. of Tokushima, Japan, A. Sakamoto - Kochi U., Japan 18:30-20:30 Banquet
Friday, November 22 8:30-10:10 Session 4: ATPG and Fault Simulation S4-1 A Novel Approach to RTL Behavioral Implication Z. Yin, H. Li, and X. Li - ICT/CAS, China S4-2 Efficient Hierarchical Test Generation for RTL Circuits Y.-J. Xue, H. Wang, S.-Y. Yang, J.-H. Xing, Y.-C. Deng - Tsinghua U., China S4-3 X-Maximal Test Set Generation for Combinational Circuits T. Hayashi, Y. Morimoto, T. Shinogi, H. Kita, H. Takase - Mie U., Japan S4-4 Using Verilog VPI for Serial Fault Simulation in a Test Generation Environment P. A. Riahi, Z. Navabi, F. Karimi, F. Lombardi - Northeastern U., USA 10:10-10:40 Coffee Break 10:40-11:55 Session 5: Effectiveness in Test S5-1 A Test Plan Grouping Method to Reduce Test Length and Test Controllers for RTL Data Paths T. Hosokawa, H. Date, M. Miyazaki, M. Muraoka - STARC, Japan S5-2 Test Data Volume Reduction Using Statistical Encoding for Multiple Scan Chain Designs K. Taniguchi, K. Miyase, S. Kajihara - Kyushu Inst. of Tech., Japan, I. Pomeranz - Purdue U., USA, S. M. Reddy - U. of Iowa, USA S5-3 On Effective Criterion of Path Selection for Delay Testing M. Fukunaga, S. Kajihara - Kyushu Inst. of Tech., Japan, S. Takeoka, S. Yoshimura - Matsushita Elec., Japan 11:55-12:00 Closing Remark |