Technical Program
November 20
Opening & Invited talk: Extending the Reach of Hierarchical Test
Alex Orailoglu - University of California, San Diego, USA
November 20, 8:30 - 9:25
Session 1-BIST
November 20, 9:40 - 11:45
Chair : Kewal Saluja
1.1 : A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead
Abdil Rashid Mohamed, Zebo Peng and Petru Eles
1.2 : On the non-scan BIST schemes under power constraints for RTL data paths
Zhiqiang You, Michiko Inoue, Hideo Fujiwara
1.3 : On Complete Deterministic Testing Logic in BIST for High Availability systems
V.Mahalingam
1.4 : A RTL-level BIST Structure for a Remote Sensing Satellite ASIC
Xiaodong Xie
1.5 : Fast and Efficient Test-Point Selection Algorithm for Scan-Based BIST
Hu He, Yihe Sun
November 20, 12:00 - 13:30
Lunch
Steering Committee Meeting (members only)
Session 2-ATPG
November 20,13:30 - 15:30
Chair : Michiko Inoue
2.1 : An improvement of a test plan generation algorithm for hierarchical test based on strong Testability
Tomoo Inoue, Naoki Okamoto, Hideyuki Ichihara, Toshinori Hosokawa, Hideo Fujiwara
2.2 : VRM: Verilog RTL Model for High-Level Testing
Li Shen
2.3 : Verilog RTL Model Based Concurrent Fault Simulation
Li Shen
2.4 : Controller Testing Using Combination of GAs and Symbolic Methods
Reihaneh Saberi, Elham Safi and Zainalabedin Navabi
2.5 : A High-Level Testing Generation Method Based on Verilog RTL Model
Yan Gao, Li Shen
Session 3- DFT
November 20,15:45 - 17:50
Chair : Tomoo Inoue
3.1 : Random Pattern Testability of Circuits Derived from BDDs
Junhao Shi, Görschwin Fey, Rolf Drechsler
3.2 : An Approach to Non-Scan Design for Delay Fault Testability of Controllers
Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
3.3 : Testability Analysis Algorithm of Behavioral VHDL Description
Shengbing Zhang, Deyuan Gao, Ying Li
3.4 : A New Low-Power Scan-Path Architecture
S. Hatami, E. Atoofian, A. Afzali-Kusha and Z. Navabi
3.5 : A Novel Register Allocation Method For Testability Improvement
Saeed Safari, Hadi Esmaeilzadeh, Amir Hossein Jahangir
Banquet
November 20,18:30 - 20:30
November 21
Session 4- Test Compaction
November 21,8:30 - 10:10
Chair : Masaki Hashizume
4.1 : On Test Data Compression Using Selective Don't-Care Identification
Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, and Haruhiko Takase
4.2 : Compaction Network design for Feedback-Free MISR
Yinhe Han, Huawei Li, and Xiaowei Li
4.3 : A Novel Partition-based Technique to Reduce the Power, Time and Data Volume in Scan-based Test
Mohammad Hosseinabadi, Shervin Sharifi, Zainalabedin Navabi
4.4 : Test Length Minimization under Power Constraints for Combinational Circuits
Hao Wu, Zhiqiang You, Michiko Inoue, Hideo Fujiwara
Session 5- Functional Verification
November 21,10:25 - 12:00
Chair : Xiaodon Xie
5.1 : Property Classification for Hybrid Verification
Ming Zhu , Jinian Bian, Weimin Wu, Hongxi Xue
5.2 : ACSAT: A SAT Solver via Solving TSP by ACO
Jianzhou Zhao, Jinian Bian
5.3 : Combining SystemC with Unit Test for System Level Verification of SoC
Yan Chen, Bo Zhou, Weidong Qiu, Chenglian Peng
5.4 : A WGL Verification Approach Based on Polynomial Symbolic Manipulations
Zhen-Jun Du, Guang-Sheng Ma, Gang Feng
5.5 : Safety Checking By Problem Solving
Weimin Wu, Di Wang, Weiwei Zheng, Jinian Bian, Ming Zhu
November 21,12:00 - 13:30
Lunch
Session 6- SOC Testing
November 21,13:00 - 15:10
Chair : Weikang Huang
6.1 : A New Strategy and Design For Mixed Signal SOC Testing
C.V.Guru Rao, Debdeep Mukhopadhyay, D.Roy Chowdhury
6.2 : A Test Access Mechanism Interfacing with IEEE 1149.1 TAP for Testing IP Based System-on-a-Chip
Yong-sheng Wang, Li-yi Xiao, Ming-yan Yu, Jin-xiang Wang, Yi-zheng Ye
6.3 : A Genetic Testing Framework for Self-Testing of Microprocessor Cores
Elham Safi , Reihaneh Saberi and Zainalabedin Navabi
6.4: Fast and Efficient Test-Point Selection Algorithm for Scan-Based BIST
Hu He, Yihe Sun
Session 7- Fault Diagnosis & On-line Testing
November 21,15:25 - 16:40
Chair : Jinian Bian
7.1 : Efficient RT-level Diagnosis Methodology
Ozgur Sinanoglu and Alex Orailoglu
7.2 : Error Detection and Correction in VLSI Systems by complementary logic and alternating-retry
Jianhui Jiang
7.3 : Preliminary Study Towards the EMI-Induced Bit-Flips Prediction for COTS Microprocessors
Fabian Vargas, Diogo Becker Brum, Danniel Cavalcante Lopes
7.4 : A Sufficient Condition for Pessimistically t/t Diagnosable Systems with Application to Cube-Connected Systems
Xiaofan Yang, Graham M. Megson
----------------------------------- |