WRTLT'04 Technical Program
5th Workshop on RTL and High Level Testing November 11-12, 2004, International House, Osaka, Japan Held in conjunction with the 13th Asian Test Symposium (ATS'04)
Abstracts are available by clicking the session titles.
November 10, 2004.
Reception (18:00-20:00)
November 11, 2004.
Opening (9:00-10:00)
Keynote Speech
Open Architecture Test System: The new frontier in test Rochit Rajsuman -- Advantest America Corporation, USA
Coffee Break
Session 1 SoC Testing (10:25-11:40)
Co-chairs: Xiaowei Li -- CAS, China, Terumine Hayashi -- Mie Univ., Japan.
S1.1
SOC Test Design Including Selection of Cores and Tests Erik Larsson* -- Linko¨pings Universitet, Sweden
S1.2
Serial and Parallel TAM Designs for System-on-Chip Interconnects Based on 2-Pattern Testability Yuusuke Saga*, Tomokazu Yoneda , and Hideo Fujiwara -- NAIST, Japan
S1.3
Design of Online Testing for SoC Using Reconfigurable Hardware and Boundary Scan Chain Abderrahim Doumar1, Kentaroh Katoh*2, Hideo Ito2 -- 1 Alakhawayn Univ., Morocco, 2 Chiba Univ., Japan
Lunch / Steering Committee Meeting
Session 2 High Level Test and Verification (13:20-14:55)
Co-chairs: Tsin-Yuan Chang -- National Tsing Hua Univ., Taiwan, Hideo Tamamoto -- Akita Univ., Japan.
S2.1
A Novel Vector Generation Method for Observability-Enhanced Statement Coverage Wei Lu*, Tao Lv, Xiu-Tao Yang, and Xiaowei Li -- CAS, China
S2.2
An RT-Level Vector Generation Scheme Using Hybrid Genetic Algorithms Wei Lu*, Xiu-Tao Yang, and Xiaowei Li -- CAS, China
S2.3
Simulation-Based Validation of VHDL Descriptions Using Constraints Logic Programming Christophe Paoli*, Marie-Laure Nivet, Fabrice Bernardi, and Laurent Capocchi -- University of Corsica, France
S2.4s
Tests Calculation for Logic and Timing Faults Jo´sef Sziray* -- Sze´henyi University, Hungary
Coffee Break
Session 3 Test Compression (15:20-16:50)
Co-chairs: Erik Lasson -- Linko¨pings Universitet, Sweden, Masaki Hashizume -- Univ. of Tokushima, Japan.
S3.1
A Test Compression Algorithm for Reducing Test Application Time Michihiro Shintani*, Toshihiro Ohara, Hideyuki Ichihara, and Tomoo Inoue -- Hiroshima City Univ., Japan
S3.2s
On Generating Test Data with High Compressibility Naohiro Hiraiwa*, Terumine Hayashi , Tsuyoshi Shinogi, Haruhiko Takase, and Hidehiko Kita -- Mie Univ. , Japan
S3.3s
A Binary Wavelet Test Compression Mohammad Hosseinabady, Pejman Lotfi-Kamran, Ardavan Pedram*, and Zainalabedin Navabi -- Univ. of Tehran, Iran
S3.4
On Extraction of a Cube with the Minimum Number of Literals from a Given Input Vector Kohei Miyase*1, Shinobu Nagayama1, Seiji Kajihara1, Xiaoqing Wen1, and Sudhakar M. Reddy2 -- 1 Kyushu Institute of Technology, Japan, 2 Univ. of Iowa, USA
Break
Session 4 BIST (17:10-18:00)
Co-chairs: Samiha Mourad -- Santa Clara Univ., USA, Kazuhiko Iwasaki -- Tokyo Metropolitan Univ., Japan.
S4.1
Defect Level vs. Yield and Fault Coverage in the Presence of an Imperfect BIST Yoshiyuki Nakamura*1,2, Jacob Savir3, and Hideo Fujiwara1 -- 1 NAIST, Japan, 2 NEC Electronics Corporation, Japan, 3 NJIT, USA
S4.2
MCBIST: A New On-Line BIST Scheme Mohammad Alisafaee, Pejman Lotfi-Kamran, Saeed Shamshiri, Hadi Esmaeilzadeh, Ardavan Pedram*, and Zainalabedin Navabi -- Univ. of Tehran, Iran
Banquet (18:30-20:30)
November 12, 2004.
Session 5 Special Session (9:15-10:00)
Chair: Tsuyoshi Shinogi -- Mie Univ., Japan.
Embedded Tutorial Shortening the Design Cycle in Nanotechnology Era: Hybrid Timing Analysis Samiha Mourad*, and Rajeev Srivastava -- Santa Clara Univ., USA
Coffee Break
Session 6 Processor Test (10:25-11:40)
Co-chairs: Richard Ruzicka -- Brno Univ. of Technology, Czech, Yasuo Sato -- STARC, Japan.
S6.1
Functional Path Delay Fault Test Flow for Processor and ASICs in SoC Jeng-Reng Huang, Min-Jun Hsiao, Po-Lin Chen, Po-Shung Huang, and Tsin-Yuan Chang* -- National Tsing Hua Univ., Taiwan
S6.2
Instruction-Based Path Delay Test Generation for Processors Hongxia Fang*, Huawei Li , and Xiaowei Li -- CAS, China
S6.3
Instruction-Based Self-Test for Sequential Modules in Processors Michiko Inoue*1, Kazuko Kambe1, Naotaka Hoashi2, and Hideo Fujiwara1 -- 1 NAIST, Japan, 2 Sony LSI Design Inc.
Lunch
Session 7 Design for Test Cost Reduction (13:00-14:40)
Co-chairs: Rochit Rajsuman -- Advantest America Corporation, USA, Hiroshi Takahashi -- Ehime Univ., Japan.
S7.1
Test Vector Overlapping for Test Cost Reduction in Parallel Testing of Cores with Multiple Scan Chains Tsuyoshi Shinogi*, Yuki Yamada, Terumine Hayashi , Tomohiro Yoshikawa, and Shinji Tsuruoka -- Mie Univ., Japan
S7.2
Interleaved Scan-Cell Architecture for Low Power Test Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Eiman Ebrahimi, Ardavan Pedram*, and Zainalabedin Navabi -- Univ. of Tehran, Iran
S7.3
DFT Signoff at RTL Using Predictive Analysis Technique Douglas Kay1, Young Lee1, Sung Chung1, and Ralph Marlett*2 -- 1 Cisco Systems, USA, 2 Atrenta, USA
S7.4
Low-Power Board-Mounted Reconfigurable Tester Based on HDL Descriptions Masayuki Sato1, Nobuyuki Otsuka2, Osamu Muto2, Masayuki Arai*1, Satoshi Fukumoto1, Kazuhiko Iwasaki1 , Koji Uehara3, Isao Shimizu3, and Haruo Mamyouda3 -- 1 Tokyo Metropolitan University, Japan, 2 INNOTECH Corp., Japan, 3 Renesas Technology Corp., Japan
Closing (14:40-14:50)
s: short presentaiton, *: speaker. -----------------------------------
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