WRTLT Head Graph
6th Workshop on RTL and High Level Testing, WRTLT`05
Call for papers

Call for Papers
6th Workshop on RTL and High Level Testing
July 20-21, 2005, Harbin, China
Sponsored by
IEEE Computer Society Test Technology Technical Council
In cooperation with
Technical Committee on Fault Tolerant Computing, CCF

High level testing is an important topic in the SoC age. The sixth WRTLT will bring together the researchers and designers in the field from all over the world. The workshop aims to provide a forum for them to exchange ideas and experiences on register transfer level (RTL) and high level testing.
Papers are invited on the topics related to, but not limited to, the following areas:
● High Level Testing
● Processor Testing
● Software Testing
● SoC Testing
● Functional Verification

Authors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper and should include: title, full name and affiliation of all authors, 50 words abstract and keywords. Please submit papers as postscript or pdf files to the following address by March 30, 2005.
Please identify the contact author and include the complete mailing address, email address, telephone and/or fax numbers of the author. Authors will be notified of acceptance by May 10, 2005.Camera-ready papers should be submitted to the same address by June 10, 2005.

Submission deadline: March 30, 2005.
Acceptance notification: May 10, 2005.
Camera-ready due: June 10, 2005
Photocopies of accepted papers will be handed out to the attendees at the workshop site.
For up-to-date information on WRTLT'05, please visit the workshop website: http://wrtlt05.hit.edu.cn. Or contact the workshop

WRTLT 2005 Technical Program

July 20-21, 2005,SINOWAY Hotel, Harbin, China

July 19, 2005

08:00-18:00 Registration Open at SINOWAY Hotel

18:00-20:00 Welcome Reception

July 20, 2005

08:00-08:30 Opeining Session

08:30-10:00 Session 1 BIST
Co-Chairs: Yinghua Min, Insitute of Computing Technology, Chinese Academy of Sciences, China
Tomoo Inoue, Hiroshima City University, Japan

1.1 : Perfect error identification in at-speed BIST environment
   Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja and Hideo Fujiwara
1.2 : Test Data Compression Using TPG Reconstruction for BIST-Aided Scan Test
   Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki,Takahisa Hiraide and Takashi Aikyo
1.3 : Localizing Test Power Consumption for Scan
   Dong Xiang, Kai-wei Li and Hideo Fujiwara
1.4 : Matrices of Multiple Weights for Test Response Compaction with Unknown Values
   Thomas Clouqueur, Kewal K. Saluja and Hideo Fujiwara
1.5 : A Memory Grouping Method for reducing Memory BIST Logic of System-on-Chips
   Masahide Miyazaki, Tomokazu Yoneda and Hideo Fujiwara

Coffee Break

10:15-11:45 Session 2 ATPG
Co-Chairs: Hideo Tamamoto, Akita University, Japan
Dafan Zhang, Hunan University, China

2.1 : A Method for Low-Capture-Power At-Speed Scan Test Generation
   Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima and Seiji Kajihara
2.2 : Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability
   Masato Nakazato Satoshi Ohtake and Hideo Fujiwara
2.3 : Test Generation Complexity for Path Delay Faults Based onNotation
   Chia Yee OOI, Thomas CLOUQUEUR and Hideo FUJIWARA
2.4 : Test data sequence generation method for Reduced Scan Shift without scan chain flip-flop reordering
   Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa and Shinji Tsuruoka
2.5 : Test Generation for Scan Circuits Using Random Selection of the Operations of Scan Flip-flops
   Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada
2.6 : A Novel Method to Identify Sensitized Paths Certainly
   LEI Shaochong and SHAO Zhibiao

12:00-13:30 Lunch / Steering Committee Meeting

13:30-15:00 Session 3 SoC Testing
Co-Chairs: Hiroyuki Yotsuyanagi, University of Tokushima, Japan
Xiaowei Li, Institute of Computing Technology, Chinese Academy of Sciences, China

3.1 : A Test Data Compression Architecture with Abort-on Fail Capability
   Erik Larsson and Giliani Irtiyaz
3.2 : An Efficient Detect Model for Crosstalk Faults on SOC interconnects.
   ZHANG Jin-Lin, SHEN Xu-Bang and CHEN Chao-Yang
3.3 : Evaluation Dependability of SoC by Software Method
   Jun-jie Peng1, Bing-rong Hong, Rui Li and Cheng-jun Yuan
3.4 : A new and Efficient Model for Testing Signal Integrity in SoCs
   ZHANG Jin-Lin, SHEN Xu-Bang and CHEN Chao-Yang
3.5 : A Reseeding BIST Scheme with Variable Lengths of Test Sequence
   YANG Zheyi, ZHANG Jiansheng, HUANG Weikang


15:05-15:30 Session 4 Software Testing
Chair: Yongshen Wang, Harbin Institute of Technology, China

4.1 : Test suit Reduction Based on Test History
   Xue-ying MA and Cheng-qing YE
4.2 : The Software/Hardware Co-Debug Environment with Emulator
   Baodong Yu and Xuecheng Zou

Coffee Break

15:45-16:50 Session 5 High Level Testing
Chair: Xiaoqing Wen, Kyushu Institute of Techonlogy, Japan

5.1 : A Functional Test Method for State Observable FSMs
   Toshinori Hosokawa and Hideo Fujiwara
5.2 : The Reseeding Timing for a 32-bit Digital Chaos-Based Pseudo Random Number Generator
   Jiung-Sheng Chen, Chung-Yi Li and Tsin-Yuan Chang
5.3 : ADC BIST Based on Linear Histogram Using Parallel Time Decomposition
   WANG Yong-sheng, XIAO Li-yi and YE Yi-zheng
5.4 : SOFM: A Novel Approach to Direct ATPG
   Xiutao Yang, Wei Lu and Xiaowei Li


16:55-18:00 Session 6 Processor Testing
Chair: Terumine Hayashi, Mie University, Japan

6.1 : A High Performance Instruction Set Simulator Using Dynamic Decode Cache
   Sang Shengtian
6.2 : Taxonomy and new trends in Fault Tolerant Modern Microprocessors
   Fu Zhongchuan ,Chen Hongsong ,Yang Hua and Cui Gang
6.3 : THUMPSim: A Cycle Accurate Processor Simulator
   Yu Gu, Youhui Zhang and Dongsheng Wang
6.4 : Memory System Testing Technology of Chip Multiprocessor
   Guo Songliu, Li Zhaolin and Wang Dongsheng

18:30-20:30 Banquet

July 21, 2005

8:30-10:00 Session 7 RTL DFT
Co-Chairs: Erik Larsson, Linkoepings University, Sweden
Jinian Bian, Tsinghua University, China

7.1 : A method for designing hierarchically testable datapaths based on fixed-control testability
   Tomoo Inoue, Yudai Kawahara and Hideyuki Ichihara
7.2 : A Built-In Self-Repair Compiler for Embedded Memories Based on VDWL Architectures
   Shyue-Kung Lu and Shih-Chang Huang
7.3 : A Low Power Deterministic Test Using Scan Chain Disable Technique
   Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara
7.4 : On Quantifying Observability for Fault Diagnosis of VLSI Circuits
   Naoya Toyota, Xiaoqing Wen, Seiji Kajihara and Masaru Sanada
7.5 : Estimating Power Consumption Increase due toTestability Enhancement in RTL Domain
   Naghmeh karimi and Mehdi Sedighi

Coffee Break

10:15-12:00 Session 8 Functional Verification
Co-Chairs: Weikang Huang, Fudan University, China
Tsin-Yuan Chang, National Tsing Hua University, Taiwan, China

8.1 : Sequential Equivalence Checking Combining BDD and Sequential SAT
   Feijun Zheng and Xiaolang Yan
8.2 : Hierarchical Property Checking for RTL Circuits by LP-based Satisfiability Solving
   Weiwei Zheng, Weimin Wu and Jinian Bian
8.3 : Model Checking of A DLX Microprocessor Design By Exploiting Modular Hierarchy
   Di Wang, Weimin Wu, Weiwei Zheng and Jinian Bian
8.4 : Research on the FSM-Based Automatic Generation Method of Monitor in Functional Verification
   Zhang Duoli, Li Li and Gao Minglun
8.5 : Finding Optimized Verification Path in SoC FSM
   WANG Zhonghai and YE Yizheng
8.6 : Hierarchy Testbench Design Method for IP Block Functional Verification
   Yang Minhua, Li Li , Sha Jin, Gao Minglun and Li Wei

12:00-13:30 Lunch

13:30-17:30 A tour of the city

General Chair:
Zhigang Mao
Harbin Institute of Technology
Program Chair:
Liyi Xiao
Harbin Institute of Technology
Finance Chair:
Yongsheng Wang
Harbin Institute of Technology
Local Arrangement Chair:
Fengchang Lai
Harbin Institute of Technology
Registration Chair:
Jinxiang Wang
Harbin Institute of Technology
Yunlong Bi
Harbin Institute of Technology

Steering Committee
Hideo Fujiwara, Japan
Terumine Hayashi, Japan
Kazuhiko Iwasaki, Japan
Xiaowei Li, China
Alex Orailoglu, USA
Kewal K. Saluja, USA
Hideo Tamamoto, Japan
J. Paulo Teixeira, Portugal
Dafang Zhang, China

Program Committee
Dafang Zhang , China
Erik Larsson , Sweden
Hiroyuki Yotsuyanagi,Japan
Huawei Li , China
Jianhui Jiang , China
Jinian Bian , China
Kazumi Hatayama , Japan
Kewal K. Saluja , USA
Masaki Hashizume , Japan
Matteo Sonza Reorda,Italy
Michiko Inoue , Japan
Satochi Fukumoto , Japan
Sying-Jyan Wang,Taiwan,China
Terumine Hayashi , Japan
Tomoo Inoue , Japan
Tsuyoshi Shinogi , Japan
Weikang Huang , China
Xiaoqing Wen , Japan
Xiaowei Li , China
Yihe Sun , China
Yingquan Zhou , China
Yongsheng Wang , China
Zhongcheng Li , China