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Final Program November 23 12:30 - 14:00 Welcome Lunch 4F Institute of System LSI Design Industry 14:00 - 15:00 Opening session Welcome Messages Kazuhiko Iwasaki, General Chair Michiko Inoue, Program Chair WRTLT’05 Best Paper Award Presentation Invited Talk Low Power Testing Christian Landrault (LIRMM - France) 15:00 - 15:10 Break 15:10 - 16:10 Session 1 RTL Testing Chair: Tsin-Yuan Chang - National Tsing Hua University, Taiwan 1.1 A New Non-Scan DFT Method Based on the Time Expansion Model for RTL Controller-Datapath Circuits Hiroyuki Iwata*, Tomokazu Yoneda and Hideo Fujiwara (Nara Institute of Science and Technology - Japan) 1.2 Fault Dependent / Independent 2-Pattern Test Generation Methods for State Observable FSMs Toshinori Hosokawa* 1, Ryoichi Inoue 1 and Hideo Fujiwara 2 (1 Nihon University - Japan, 2 Nara Institute of Science and Technology - Japan) 16:10 - 16:30 Coffee Break 16:30 - 18:00 Session 2 SoC Testing Chair: Huawei Li - Chinese Academy of Sciences, China 2.1 An Optimal Test Bus Design for Transparency-based SoC Test Tomokazu Yoneda* 1 Akiko Shuto 2, Hideyuki Ichihara 3, Tomoo Inoue 3 and Hideo Fujiwara 1 (1 Nara Institute of Science and Technology - Japan, 2 Sony Semiconductor Kyushu Co., Ltd. - Japan, 3 Hiroshima City University - Japan) 2.2 Test-length selection and TAM optimization for wafer-level, reduced pin-count testing of core-based digital SoCs Sudarshan Bahukudumbi and Krishnendu Chakrabarty* (Duke University - USA) 2.3 A Delay Fault Testing Framework on Core-Based System-on-Chip Po-Lin Chen*, Hao-Hsuan Chiu and Tsin-Yuan Chang (National Tsing Hua University - Taiwan) 19:00 - 21:00 Banquet PENTHOUSE 34 34 F JAL Resort Sea Hawk Hotel Fukuoka November 24 8:45 - 10:00 Session 3 Low Power Testing and Diagnosis Chair: Kazumi Hatayama − STARC, Japan 3.1 Designing Power-aware Wrappers for Multi-clock Domain Cores Using Clock Domain Partitioning Thomas Edison Yu* 1, Tomokazu Yoneda 1, Danella Zhao 2 and Hideo Fujiwara 1 (1 Nara Institute of Science and Technology - Japan, 2 University of Louisiana at Lafayette - USA) 3.2s PowerCut - A novel low-power scan testing Wei Wang 1,2, Yin-He Han 2, Xiao-Wei Li 2, You-Sheng Zhang 1, Yu Hu* 2 and Hua-Wei Li 2 (Hefei University of Technology - China, 2 Chinese Academy of Sciences - China) 3.3 An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits Xiaoqing Wen 1, Yuta Yamato* 1, Kohei Miyase 2, Seiji Kajihara 1, Hiroshi Furukawa 1, Laung-Terng Wang 3, Kewal K. Saluja 4 and Kozo Kinoshita 5 (1 Kyushu Institute of Technology - Japan, 2 Innovation Plaza Fukuoka, Japan Science and Technology Agency - Japan, 3 SynTest Technologies - USA, 4 University of Wisconsin - Madison - USA, 5 Osaka Gakuin University - Japan) Coffee Break 10:00 - 10:20 10:20 - 12:05 Session 4 Scan Based Tesing Chair: Dong Xiang − Tsinghua University, China 4.1 Scan Chain Flip-Flop Reordering Method of Considering Wiring Length for Test Response Test Vector Overlapping Testing Tsuyoshi Shinogi*, Tadao Kyotani, Masakazu Tokairin and Terumine Hayashi, Hiroharu Kawanaka and Shinji Tsuruoka (Mie University - Japan) 4.2 A Note on Test Data Reduction Combining Illinois-Scan with Bit-Flipping Masayuki Arai*, Satoshi Fukumoto and Kazuhiko Iwasaki (Tokyo Metropolitan University - Japan) 4.3 Extended Compatibilities for Scan Tree Construction Zhiqiang You* 1, Michiko Inoue 2 and Hideo Fujiwara 2 (1 Hunan University - China, 2 Nara Institute of Science and Technology-Japan) 4.4s Test Time Reduction for Scan Circuits by Selection of a Flip-flop with Hold Operation Hiroyuki Yotsuyanagi*, Tomohiko Nagashima and Masaki Hashizume (The University of Tokushima - Japan) 12:05 - 13:30 Lunch 4F Institute of System LSI Design Industry 13:30 - 15:00 Session 5 Verification and DFT Check Chair: Ilia Polian − University of Freiburg, Germany 5.1 Combining ATPG and SAT for Preimage Computation in Unbounded Model Checking Lingyi Liu, Yang Zhao, Tao Lv, Huawei Li* and Xiaowei Li (Chinese Academy of Sciences - China) 5.2s Epistasis Reducing through Constraint Propagation in Satisfiability Solving Using Genetic Algorithm Shujun Deng, Weimin Wu, Jinian Bian* and Xiaoqing Yang (Tsinghua University - China) 5.3s Model Checking of Microprocessors in Verilog using HDPLL Xiaoqing Yang, Jinian Bian* and Shujun Deng (Tsinghua University - China) 5.4s Assertion Efficiency Assessment Method M. Riazati, S. Mohammadi and Z. Navabi* (University of Tehran - Iran) 5.5s The Importance of RTL DFT Check In ASIC Design Wei Tee Ng*, Chin Hu Ong and Boon Hui Ang (Marvell Semiconductor - Malaysia) 15:00 - 15:20 Coffee Break 15:20 - 16:35 Session 6 Self-Test and Memory Test Chair: Krishnendu Chakrabarty - Duke University, USA 6.1 Deterministic Circular Self Test Path Ke Wen, Yu Hu* and Xiaowei Li (Chinese Academy of Sciences - China) 6.2s At-Speed Test of Bus Interconnects in Microcomputers Eiji Tasaka 1, Masaki Hashizume* 2, Seiichi Nishimoto 2 , Hiroyuki Yotsuyanagi 2, Takahiro Oie 2, Ikuro Morita 2 and Toshihiro Kayahara 1 (1 Miura Co. Ltd., - Japan, 2 The University of Tokushima - Japan) 6.3s March tests for two-port DRAMs Wang Ying 1,2,3, Wang Hong 1, Li Jinfeng 3 Lv Yan* 1 and Yang Zhijia 1 (1 Chinese Academy of Sciences - China, 2 Graduate University of Chinese Academy of Sciences - China, 3 Shenyang Institute of Chemical Technology - China) 6.4s Low-Power Built-In Self-Test Techniques for Embedded SRAMs Shyue-Kung Lu, Chia-Hsiu Liu*, Chun-Lin Yang and Yuang-Cheng Hsiao (Fu Jen Catholic University - Taiwan) 16:35 - 16:40 Closing session Announcement of WRTLT’07 *Presenter
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