Advanced Program

Advanced Program(PDF) (Updated on Nov. 18)

Day 1: Thursday, Nov. 24, 2016

12:00Bus Service from ATS’16 Venue to WRTLT’16 Venue
13:00Welcome Lunch
14:20Plenary Session
Opening
Keynote Speech
Invited Talk
16:30Session 1: System Test and 3D-IC Test
17:30Session 2: Power-Aware Testing
19:00Banquet
-21:00

Day 2: Friday, Nov. 25, 2016

6:00Tour to the Miyajima Island (A World Heritage Site)
-8:00
9:00Session 3: RTL Design and Test
10:35Session 4: Field Test and Aging Analysis
11:45Invited Talk
12:10Lunch break
13:40Session 5: Advanced Scan Architecture
14:30Panel Session
16:00Closing and Group Photo
Tea Ceremony


Keynote Speech (Nov.24)
“Automatic generation of test programs from high-level processor descriptions: an academic dream?”
Prof. Matteo Sonza Reorda (Politecnico di Torino, Italy)
ABSTRACT:
The usage of functional programs to test processors is popular in several scenarios. However, these test programs often come from the re-use of application code or from random generation. In some cases, they are manually generated to achieve a given coverage value with respect to some target metric. Clearly, automating the generation process would be highly desirable, especially if we could start from a high-level description of the target processor. The talk will highlight the state of the art, identify the main obstacles and challenges, and emphasize the research opportunities in this area.
Invited Talk (Nov.24)
“Why Open Defects Should be Explicitly Targeted During Test”
Prof. Adit D. Singh (Auburn University, USA)
ABSTRACT:
New cell-aware test methods have recently received much publicity because of their success in screening significant defectivity missed by traditional stuck-at and transition delay fault (TDF) testing. For example, at ITC 2012, Hapke et al. reported 885 DPPM test escapes in a 32 nm notebook processor part despite industrial strength stuck-at and 5-detect TDF testing. Importantly, most of these test escapes were observed to cause failure in actual system application, pointing to a potentially serious field reliability issue. Careful analysis indicates that the large majority of the additional fallout from cell aware tests are open defects. In this presentation we make the case that intra gate open defects should be directly targeted during ATPG aimed at generating the most cost effective test sets. Since two-pattern tests for open defects also cover corresponding TDFs, the increase in test set size over current stuck-at and TDF is modest, while such tests can significantly improve actual defect coverage in production. Additionally, if very low defect levels are required, hazard activated opens that appear redundant in steady state signal analysis, must also be targeted. Efficient testing for these defects is more challenging and remains an open research problem.
Invited Talk (Nov.25)
“Multi-Level High-Throughput Simulation for Design & Test Validation”
Prof. Hans-Joachim Wunderlich (University of Stuttgart, Germany´╝ë
ABSTRACT:
Design and test validation is one of the most important and complex tasks within modern semi-conductor product development cycles. Both tasks analyze a design with respect to certain validation targets to ensure the compliance with given specifications or requirements, for instance timing, power, or test and product quality. The type of specification can range from abstract high-level functional behavior of the circuit down to constraints of parameters at lower levels, such as peak power consumption or transistor stress. With process scaling, not only variations but also more complex defect mechanisms have to be considered in simulation, requiring models and algorithms for analysis of effects at switch or even electrical level. Yet, state-of-the-art algorithms for the required model accuracy rely on compute-intensive simulations that do not scale to the dimensions of current and future designs. Over the past years, data-parallel architectures, such as Graphics Processing Units (GPUs), have evolved and introduced the many-core paradigm. Scalable simulation algorithms optimized for such architectures provide very high throughput allowing for the first time exhaustive timing-accurate fault simulation or switch-level simulation for large circuits, for instance. This is enabled by careful abstraction in the modeling and by tailoring the algorithmic kernels to the many-core features. Current research aims at further increasing the modeling accuracy and at hybrid approaches that employ models at different abstraction levels.
Panel Session (Nov.25)
“Quo vadis high-level test?”
Organizer: Prof. Jaan Raik (Tallinn UT, Estonia)
Panelist: Prof. Bernd Becker (Freiburg University, Germany)
Prof. Virendra Singh (Indian Institute of Technology Bombay, India)
Prof. Toshinori Hosokawa (Nihon University, Japan)
Dr. Artur Jutman (Testonica Lab, Estonia)
ABSTRACT:
The panel will focus on future trends and use cases of high-level test. The topic of higher abstraction levels to improve the scalability of test generation was a promise in 1990s and early 2000s. However, industry adoption of applying high-level test in design automation has been slow. Are there any trends that could renew the boom of high-level testing? Will there be emerging new standards to support test automation at higher abstraction levels? If so then what will be the future applications of high-level test techniques? A group of distinguished experts from the academy and industry will share there knowledge on these as well as other related questions at the WRTLT’16 panel discussion.