The purpose of this workshop is to bring researchers and practitioners of LSI testing from all over the world together to exchange ideas and experiences in register transfer level (RTL), high level and system level testing. WRTLT 2020, the twenty-first workshop, will be held in conjunction with the 29th Asian Test Symposium (ATS 2020) by a virtual conference. The workshop aims to encourage the presentation and discussion of truly innovative and ”out-of-the-box” ideas aimed at addressing the challenges of high level test. We hope and expect this workshop will provide an ideal forum for discussion on this important topic for future system-on-a-chip (SoC) devices.
Original papers on, but not limited to, the following areas are invited.
- RTL fault modeling, ATPG, DFT, BIST
- High-level fault modeling, testing and synthesis for testability
- Functional fault modeling and test bench generation
- 3D IC testing
- SoC/NoC testing, test scheduling, core-based testing, interconnect testing
- Reliable SoC, system level reliability, self-repair, fault tolerant SoC
- Microprocessor testing, design verification
- Low power testing and Test compression
- Hardware trojan detection and secure testing
Authors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper (4-6 pages, two columns). The submission should include title, full name, and affiliation of all authors, 50 words abstract, keywords and the name of contact author, in a standard IEEE two-column format. The submission will be considered evidence that upon acceptance the author(s) will present the paper at the workshop. Digest of Papers will be handed out at the workshop. All submissions are now to be made electronically through the Easy Chair conference system. Detailed instructions for submissions are to be found from the website.
- Submission deadline: August 24, 2020
- Notification of acceptance: September 25, 2020
- Camera ready manuscript: October 16, 2020