WRTLT 2020 Technical Program

Virtual Workshop venue is HERE.

November 26, 2020, all times refer to the Malaysia time (MYT , UTC +8)

8.30-8.45 Opening session

8.45-9.45 Technical session #1

  • Yu-An Shih, Shi-Tang Liu and James Chien-Mo Li
    A Novel Backtrace Heuristic for Dynamic Test Compaction
  • Haruki Chaen, Ken’ichi Yamaguchi and Hiroshi Iwata
    A Proposal of Identification Method for Second-Generation Redundancy Fault
  • Kenta Nakamura, Yuta Ishiyama and Toshinori Hosokawa
    A Test Generation Method Using Information of Design for Testability at Register Transfer Level
  • Ryo Oba, Kohei Miyase, Ryu Hoshino, Shyue-Kung Lu, Xiaoqing Wen and Seiji Kajihara
    Probability of Switching activity to Locate Hotspots in Logic Circuits

9.45-10.00 Break

10.00-11.00 Technical session #2

  • Kanami Nagata, Hiroyuki Yotsuyanagi and Masaki Hashizume
    Test Time Reduction of Small Delay Testing for Scan Design with Embedded TDC
  • Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan and Hui Xu
    A Novel High Performance Scan-Test-Aware Hardened Latch Design
  • Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama and Shyue-Kung Lu
    Recovery of Defective TSVs with A Small Number of Redundant TSVs in 3D Stacked ICs

11.00-11.15 Break

11.15-12.15 Technical session #3

  • Kean Yung Hew and Lai Man Yip
    Marginality Defect Screening to Improve Silicon Quality and Test Cost
  • Yuta Shintani, Ken’Ichi Yamaguchi and Hiroshi Iwata
    An Implementation of Functional Speed Oriented Transistor-Level Scan C-element
  • Hideyuki Ichihara, Tomoyuki Adachi and Tomoo Inoue
    Experimental Evaluation of the No-Reference Test Based of False Edge Detection for Image Processing Application
  • Wei Ming Lim, Terrence Huat Hin Tan, Sook Kwan Cheah, Kian Lek Koay and Sreejit Chakravarty
    Intel Foveros Technology: DFT And HVM Test Strategy

12.15-12-30 Break

12.30-13.15 Technical session #4

  • Yoshikazu Nagamura, Masayuki Arai and Satoshi Fukumoto
    Evaluation of CNN-Based Defect Location Estimation on LSI Layouts
  • Nikolaos Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Marcello Traiola and Emanuele Vale
    Achieving Reliability via Security Mechanisms in Artificial Neural Networks
  • Wen Li, Ying Wang, Huawei Li and Xiaowei Li
    A Novel Framework for Protecting Deep Neural Networks on ReRAM-based Deep Learning Accelerators

14.00-14.45 Keynote session – Dr. Davide Appello, STMicroelectronics

Using System Level Test to screen Automotive products: test the IC in the system before the system tests your IC

14.45-15.00 Break

15.00-15.45 Invited talk session – Mr. Terrence Tan, Intel

15.45-16.00 Break

16.00-16.50 Industrial experience session

  • Mohd Faiz Mohd Asri, Zuriel Zamir and Humberto Gamez
    A new ATE run-time library based on modern software development philosophies.
  • Eng Chin Beh, Eng Yew Liew, Chung Shen Yeoh, Nuur Azzreen Kassim and Shi Gin Teng
    Test Time Breakthrough In MCP Product With New Parallel Test Methodology Without Coverage Loss
  • Chin Keat Teoh and Swee Khing Ang
    Tackling Analog DPM with System-Level Testing
  • Wai Loon Yip, Hock Thien Ng and Bian Sim Teo
    Pre silicon validation methodology breakthrough for 3D IC
  • (Withdrawn) Muhammad Naziri Zakaria
    Cost Effective Screening and Debug in 3D IC Environment

16.50-17 Break

17.00-18.30 Panel session – System Level Test: the new frontier of testing or a temporary shortcut?

18.30-18.40 Closing session


  • The opening, keynote, invited, panel and closing sessions will be managed live with the Engagez Online Event Platform.
  • The technical and Industrial experience sessions will be based on pre-recorded videos and Q&A slots.
  • All attendees will be able to interact among each other during the Breaks.
  • An Informal Digest of Papers will be distributed to all attendees.
  • A Best Paper Award will be granted to a paper from the morning sessions. The winner will be announced during the Closing Session.