Welcome to WRTLT 2021

The organizing committee of WRTLT 2021 has decided to hold this symposium virtually due to the COVID-19 pandemic.

The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. WRTLT’21, the 22nd workshop, will be held in conjunction with the 30th Asian Test Symposium (ATS’21).

Areas of interest include but are not limited to:

  • RTL fault modeling, ATPG, DFT, BIST
  • High-level fault modeling, testing and synthesis for testability
  • Functional fault modeling and test bench generation
  • System Level Testing
  • 3D IC testing
  • SoC/NoC testing, test scheduling, core-based testing, interconnect testing
  • Reliable SoC, system level reliability, self-repair, fault tolerant SoC
  • Microprocessor testing, design verification
  • Low power testing and Test compression
  • Hardware trojan detection and secure testing

Key days

  • Submission deadline: August 20, 2021
  • Notification of acceptance: September 24, 2021
  • Camera-ready: October 29, 2021
  • Video submission: November 19, 2021

General information
Toshinori Hosokawa, General Chair
wrtlt2021japan<at>gmail.com