Title
Cost-effective test screening circuits for high-reliable embedded SRAMs
Speaker
Dr. Koji Nii
Senior Fellow of Green Innovation Lab.,
Kyoto Institute of Technology
Abstract
Embedded SRAMs with cost-effective test screening circuitry are demonstrated for low-power microcontroller units (MCUs). The probing test step at the low temperature (LT) of -40°C is obviated by imitating pseudo-LT (PLT) conditions in the package test, where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out considering local Vt variations as well as contact soft open failure (high resistance), confirming good minimum operating voltage (Vmin) correlation between LT and PLT conditions. Test chips with two types of 4-Mbit single-port SRAM macros and 1-Mbit dual-port SRAM macro are designed and fabricated using low-power 40-nm CMOS technology. Measurement results demonstrate that the proposed test method reproduces LT conditions and screens out LT failures with less overscreening. The proposed test method eliminates 1/3 or more of the test costs.
Biography
Koji Nii received the B.E. and M.E. degrees from Tokushima Univ., and the Ph.D. degree from Kobe Univ. in 2008. In 1990, he joined Mitsubishi Electric Corp., and he was transferred to Renesas Technology Corp. in 2003, Renesas Electronics Corp. in 2010, where he has been worked on the research and development of embedded SRAMs, TCAMs, ROMs on 28nm to 0.8um bulk/SOI CMOSs and advanced 7-16nm FinFETs. In 2018, he joined Floadia Corp., which is an embedded Flash IP company in Tokyo.
He is now with TSMC Design Technology Japan, Inc., in charge of a head of memory design team for developing advanced FinFET SRAM compilers, and custom cache SRAMs, Register files and computing-in-memory IPs. His current responsibility is Director, Japan Memory Design Program, Memory Solution Division. Dr. Nii holds over 100 US patents and over 150 papers/presentations at major int’l journals/conferences. He served Technical Program Committees of the IEEE CICC and IEDM, and an Associated Editor of the IEEE Trans. on VLSI Systems. He was also a Visiting Professor of Graduate School of Natural Science and Technology, Kanazawa Univ. and now is a Senior Fellow of Green Innovation Lab., Kyoto Institute of Technology (2019-).