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Nov. 25 Thu.
12:45-13:45 Keynote session
(Chair: Hideyuki Ichihara)
- CAD for (SoC) Security: Pre-silicon Security Signoff from C to GDSII
Prof. Mark Tehranipoor
(Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity. Director, Florida Institute for Cybersecurity Research, University of Florida)
14:00-15:30 Technical Session 1: Fault Diagnosis
(Chair: Shi-Yu Huang)
- Diagnosis for Interconnect Faults in Memory-based Reconfigurable Logic Device
Xihong Zhou, Senling Wang, Yoshinobu Higami and Hiroshi Takahashi
- A Don’t Care Filling Method for Control Signal Values of Controllers to Enhance Fault Diagnosability at Register Transfer Level
Kohei Tsuchibuchi, Toshinori Hosokawa and Koji Yamazaki
- An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information
Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi and Masayuki Arai
16:00-16:40 Invited talk session
(Chair: Hiroyuki Yotsuyanagi)
- Cost-effective test screening circuits for high-reliable embedded SRAMs
Dr. Koji Nii (Kyoto Institute of Technology)
17:10-18:40 Technical Session 2: Test Generation and At-Speed Testing
(Chair: Kazuteru Namba)
- Open-source Quantum Automatic Test Generator
Chin-Yang Jen, Chin-Huan Wang, Cheng-Yun Hsieh, Yu-Min Li and James Chien-Mo Li
- Evaluation of Power Consumption with Logic Simulation and Placement Information for At-Speed Testing
Taiki Utsunomiya, Kohei Miyase, Ryu Hoshino, Shyue-Kung Lu, Xiaoqing Wen and Seiji Kajihara
- About the High-Level STLs Generation for In-field GPU Testing
Juan David Guerrero Balaguera, Josie Esteban Rodriguez Condia and Matteo Sonza Reorda
Nov. 26 Fri.
12:30-14:00 Technical Session 3: Self-Repair and DFT
(Chair: Huawei Li)
- Efficient Built-In Self-Repair Techniques with Fine-Grained Redundancy Mechanisms for NAND Flash Memories
Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase and Xin Dung
- An Additional State Transition Insertion Method to Improve Transition Fault Coverage for Controllers
Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki and Masayoshi Yoshimura
- Scan Shift Reduction in Delay Testing using Boundary Scan with Embedded TDC
Hiroyuki Yotsuyanagi, Koji Arimoto, Koji Makino and Masaki Hashizume
14:30-16:00 Technical Session 4: Reliability and Security
(Chair: Kohei Miyase)
- Edge Triggered D Flip-Flop Using Complementarity of DICE
Noriki Matsuura and Kazuteru Namba
- Adversarial Attack Detection and Correction using Generative Adversarial Networks
Jun-Shiuan Hsieh, Yu-Hsiang Lo, I-Wei Chiu, Hsiao-Yin Tseng and Chien-Mo Li
- A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
Atsuya Tsujikawa, Masayoshi Yoshimura and Toshinori Hosokawa
Times are JST (GMT +9:00).