Nov. 25 Thu.
| 12:30-12:45 | Opening |
| 12:45-13:45 | Keynote : CAD for (SoC) Security: Pre-silicon Security Signoff from C to GDSII |
| 14:00-15:30 | Session 1 : fault diagnosis |
| 16:00-16:40 | Invited Talk : Cost-effective test screening circuits for high-reliable embedded SRAMs |
| 17:10-18:40 | Session 2 : test generation and at-speed testing |
Nov. 26 Fri.
| 12:30-14:00 | Session 3 : self-repair and DFT |
| 14:30-16:00 | Session 4 : reliablity and security |
| 16:00-16:15 | Closing |
Times are JST (GMT +9:00).